1. Field of the Invention
The present invention relates to integrated passive devices (IPDs) which are flip bonded to one another, and more particularly, to IPDs which are flip bonded using nano junction technology, such as nanoparticle bonding bumps.
2. Description of the Related Art
Radio-frequency (RF) electrical circuits frequently use passive devices and passive device circuits. Many of these RF electrical circuits are used in hand-held wireless products. Accordingly, miniaturization of passive devices and passive device circuits is an important goal in RF device technology.
Recent advances in passive device technology have produced IPDs wherein inductors, capacitors, and resistors are integrated on a single compact substrate. IPD substrates are large and are preferably made of silicon, but in some cases are made of ceramic. IPD substrates and manufacturing methods of IPD substrates can be found in U.S. Pat. No. 7,382,056, the entire contents of which are herein incorporated by reference.
The design of inductor components in these IPDs usually has two goals: a compact space and high Q-factor. In general, inductor devices require conductors that are arranged side-by-side along a substantial length of the conductors. Current flows in the same direction through the side-by-side conductors so that the magnetic flux lines are in the same phase. This results in a large mutual inductance. Straight conductors achieve this goal in principle but require excessive linear space in a conventional IPD. Conductors that are spiral-shaped or have a configuration including nested-squares or nested-rectangles achieve the desired result in a more compact space.
The other goal, high Q-factor, seeks high performance (inductance value) with low power loss. Several factors influence the Q-factor. The inductance value depends on the length and spacing of the conductors. The power loss depends on the conductivity of the metal. The conductivity depends on the width and thickness of the conductors. Thus, several parameters are involved in the design considerations for high Q-factor inductors.
However, some of the design goals are in conflict with each other. For example, for small, compact IPDs, it is desirable to shrink the interconnections, which increases the resistance of the inductor conductors and reduces the Q-factor of the inductor. To offset this, the conductivity of the conductor can be increased by switching from aluminum, which is the standard metal used to form the conductor, to copper. Another proposal is to coat the aluminum conductors with a copper strike layer.
Another approach is to increase the length of the inductor. Nominally, it would appear that increasing the inductor length would require increased surface area. However, it has been recognized that inductor design is not restricted to two dimensions. Accordingly, three-dimensional IPDs, i.e. devices built on multiple levels, have been developed. Multiple level inductors produce multiplied inductor values for a given surface area.
With the proven advantages of two-level inductors, additional levels, for example, four levels, would appear to be the next step. However, each added level in an IPD substrate increases costs. This is especially the case where the added levels serve only the inductor elements.
An approach to constructing three-dimensional inductors for IPDs is disclosed in U.S. Pat. No. 7,355,264, the entire contents of which are herein incorporated by reference. This approach involves constructing a portion of the inductor on a base substrate and constructing a mating portion of the inductor on a cover substrate. The cover substrate is then flip bonded to the base substrate, thus mating the two portions of the inductor. Using this approach, a two level inductor can be constructed without using a multilevel substrate. Using two two-level substrates yields a four-level device.
A benefit of the approach disclosed in U.S. Pat. No. 7,355,264 is that the structure allows different substrates to be used in the two portions. Thus, a silicon IPD substrate can be used for the first portion of the inductor, and a GaAs substrate can be used for the second portion of the inductor. Other components can be built on the substrates according to the particular application. For example, high performance components can be located on the GaAs substrate, and less demanding components can be located on the silicon substrate.
In FIG. 5 of U.S. Pat. No. 7,355,264, dielectric layers 51 and 55 are formed over the metal layers 41 and 42, and contact windows 53 and 57 are formed through layers 51 and 55, exposing the metal layers 41 and 42 for electrical contacts. Windows 53 are aligned with windows 57 so that metal layer 41 and contact windows 53 form a mirror image of metal layer 42 and contact windows 57.
In FIG. 6 of U.S. Pat. No. 7,355,264, the electrical contacts 61 and 62 are formed in and on the contact windows 53 and 57. The electrical contacts 61 and 62 are solder bump contacts and can include under bump metallization (UBM). If the metal layers 41 and 42 are copper and the electrical contacts 61 and 62 are copper, then the electrical contacts 61 and 62 bond directly to the metal layers 41 and 42. However, if the metal layers 41 and 42 are aluminum, a special UBM is typically used. The usual practice is to apply a UBM coating to the metal layers 41 and 42 and apply the electrical contacts 61 and 62 (solder bumps) to the coating. The metal or metals used in UBM technology must adhere well to aluminum, be wettable by solder, and be highly conductive.
FIG. 7 of U.S. Pat. No. 7,355,264 shows solder bumps 72 applied to electrical contact 62 on cover substrate 21. Alternatively, solder bumps 71 can be applied to electrical contact 61 on the base substrate 11, or, in some cases, solder bumps 71 and 72 can be applied to electrical contacts 61 and 62, respectively, on both substrates. The solder bumps 71 and 72 are typically applied using a solder paste process.
With both of the base substrate 11 and the cover substrate 21 essentially completed, the base substrate 11 and the cover substrate 21 are assembled together, as shown in FIG. 8 of U.S. Pat. No. 7,355,264, by flip bonding the cover substrate 21 on top of the base substrate 11, by aligning the solder bumps 72 to the electrical contact 61 on the base substrate 11 (or by registering the solder bumps 71 to the electrical contact 62 on the cover substrate 11 or by registering the solder bumps 72 on the cover substrate 21 to the solder bumps 71 on the base substrate 11), and by reflowing the solder bumps 71 and 72 to attach the base substrate 11 and the cover substrate 21 together. The result is a two-level flip-bonded dual-substrate inductor.
In the IPDs disclosed in U.S. Pat. No. 7,355,264, the spacing between the IPD substrates is determined by the combination of the thickness of the dielectric layers, the thickness of the UBM, and the diameter of the solder bumps after reflow. In addition, to securely bond the IPD substrates together, the diameter of the solder bumps must be greater than a minimum diameter.
Thus, because the solder bumps must be greater than a minimum diameter, the spacing between the IPD substrates must be greater than a minimum distance. Because the spacing between the IPD substrates affects RF performance of the IPDs, the RF performance deteriorates as the spacing between the IPD substrates increases. Thus, it is difficult to achieve desired RF performance with the IPDs disclosed in U.S. Pat. No. 7,355,264. It is also a problem that, because it is difficult to ensure uniform reflow of the solder bumps, it is difficult to ensure consistent distance between the IPD substrates. If the distance between the IPD substrates is inconsistent, then the RF performance of IPD is affected.
In addition, with the solder bumps 71 and/or 72 used in U.S. Pat. No. 7,355,264, the gap between the surfaces of the base substrate 11 and the cover substrate 21 is likely to be unevenly distributed because the space between the surfaces of the base substrate 11 and the cover substrate 21 in the vicinity of one of the solder bumps 71 and/or 72 can be different from the space between the surfaces of the base substrate 11 and the cover substrate 21 in the vicinity of another one of the solder bumps 71 and/or 72. Thus, uneven distribution of the surfaces of the base substrate 11 and the cover substrate 21 deteriorates the RF performance of the IPDs.